1. Field of the Invention
This invention relates to amplifiers and more specifically to the input stage of a Class AB amplifier.
2. Description of Related Art
1. NPN, PNP Beta Mismatch
Amplifiers of the type suitable e.g. for operational amplifiers are well known in the art. Such amplifiers typically have an input stage of the Class AB type which as is well known includes at least two transistors in each buffer, one of which is a "push" (top side) transistor, the second of which is a "pull" (bottom side) transistor. Typically, one of these is a (bipolar) NPN transistor and the other is a (bipolar) PNP transistor. As is also well known, due to the intrinsic differences between P and N type semiconductor materials, the PNP transistor will have a higher beta (gain) than the NPN transistor. This asymmetry in transistor beta disadvantageously results in the output voltage not being exactly at ground level, when the bias conditions require it to be at ground.
Any output voltage present when the amplifier's output signal should be zero is conventionally termed the systematic offset voltage. This is the voltage difference that must be applied to the amplifier input (inverting and non-inverting) terminals to shift the output signal offset to zero. Typically this compensation is accomplished by providing adjustable resistances (trim resistors) to compensate for the gain differences in the two transistors. This trimming process is also called voltage offset nulling. The need to provide trimming for each individual amplifier is an additional expense in terms of amplifier fabrication. Also, the trim resistors consume (in an integrated circuit) chip "real estate".
FIG. 1 shows an amplifier having the above-described systematic voltage offset and shows the relevant current flows (each indicated by the letter I). The reference "I.sub.BP " is to the base current of a PNP transistor; the reference "I.sub.BN " is to the base current of an NPN transistor. Supply voltage Vee is equal to voltage -Vcc in this disclosure.
The inverting input buffer includes transistors Q1 and Q2 and the non-inverting input buffer includes transistors Q3 and Q4. Both the topside transistors Q1, Q3 in the input buffers and the bottom side transistors Q2, Q4 in the input buffers are connected to constant current sources respectively I.sub.1 and I.sub.2, which each source/sink a current of 2I, where I is equal to the current in the output stage flowing between the nodes at the bases of transistors Q10 and Q11. (It is to be understood that the amplifier input stage is generally to the left hand side of the drawing and the amplifier output stage to the right hand stage of the drawing.)
As can be seen, the difference between I.sub.t (the top side current through the non-inverting input buffer) and I.sub.b (the bottom side through the inverting buffer) is I.sub.b -I.sub.t =I.sub.OS which is the offset current. As can be seen by the circuit analysis, then I.sub.OS =(I-2I.sub.BN)-(I-2I.sub.BP)=2 (I.sub.BP -I.sub.BN).
Conventionally I.sub.BN is approximately equal to I/.beta..sub.N and I.sub.BP is approximately equal to I/.beta..sub.p. Thus I.sub.OS =2I(1/.beta..sub.p -1/.beta..sub.N). It is to be understood that .beta. refers to the "beta", i.e. current gain factor, of a particular transistor. Thus if .beta..sub.p =50 and .beta..sub.N =100 and I=1 mA, then I.sub.OS =20 .mu.A. Thus the offset current I.sub.OS is 20 .mu.A. As can be seen then the systematic offset voltage V.sub.OS =R.sub.E .times.(I.sub.BN -2I.sub.BP).
This offset current I.sub.OS will be reflected back to the input stage, and multiplied by the input stage gain factor g.sub.m thus creating a systematic voltage offset V.sub.OS =I.sub.OS .times.1/g.sub.m. For example if 1/g.sub.m =500 ohms, then the systematic voltage offset V.sub.OS =20 .mu.A.times.500 ohms=2.5 mV.
Another amplifier, having some similarities to that of FIG. 1 but being somewhat more complex, is shown in FIG. 2 with the accompanying current flow analysis. In this case, the input stage voltage offset is between node A and node B. Node A is associated with the non-inverting input buffer including transistors Q5-Q8 while node B is associated with the inverting input buffer including transistors Q1-Q4.
Here the difference I.sub.OS between the top side current I.sub.t and the bottom side current I.sub.b for the non-inverting input buffer is equal to I.sub.b -I.sub.t =I.sub.OS. Thus I.sub.OS =(I-2I.sub.BN)-(I-2I.sub.BP)=2(I.sub.BP -I.sub.BN). Since again I.sub.BN is approximately equal to I/.beta..sub.N and I.sub.BP is approximately equal to I/.beta..sub.p, then I.sub.OS =2I(1/.beta..sub.p -1/.beta..sub.N). Thus again if .beta..sub.p =50 and .beta..sub.N =100 and I=1 mA, then I.sub.OS =20 mA. Thus this offset current I.sub.OS .times.R.sub.E =V.sub.OS which is the systematic offset voltage.
In the amplifier of FIG. 2, the beta (gain) mismatch is in the amplifier output stage and is between the NPN transistors and the PNP transistors used in the top and bottom side modified Wilson current mirrors (respectively transistors Q.sub.11, Q.sub.12, Q.sub.14 and Q.sub.24, Q.sub.25, Q.sub.26) in the amplifier output stage. For example, as described above, NPN type transistor Q16 has a beta (gain) factor of 50, and PNP type transistor Q21 has the higher beta (gain) factor of 100. Thus the base current I.sub.BP of transistor Q16 is, given a current I of 1 mA (1000 .mu.A), equal to 20 .mu.A, and the base current I.sub.BN of transistor Q21 is 10 .mu.A. Thus the current I.sub.t at the collector of transistor Q5 is 960 .mu.A (1,000 .mu.A-40 .mu.A) and the current I.sub.b at the collector of transistor Q6 is 980 .mu.A (1,000 .mu.A-20 .mu.A). Thus this current offset causes the above-described systematic voltage offset problem which may be overcome by adding trimmable resistors (not shown) at appropriate locations such as in current mirrors Q11 to Q13 and Q23 to Q25, or by some other type of trimming operation.
It would be desirable to provide an amplifier that does not require trimming to overcome the systematic offset voltage caused by NPN, PNP beta mismatch, and which does not also require trim resistors at all, due to the accompanying undesirable extra manufacturing expense of trimming and the chip real estate consumed by the trim resistors.
2. Slew Rate Performance
A second and separate technical problem from that of the above-described NPN, PNP beta mismatch is that in a conventional voltage-feedback amplifier input stage, there is a direct relationship between the supply current and the slew rate. In a typical single stage folded cascode amplifier, the widest bandwidth is achievable while the slew rate is limited to the amount of supply (tail) current available to charge the total capacitance of the high impedance node. Since the slew rate is the supply current divided by the total capacitance, in order to obtain higher slew rates, either the supply current must be increased or the total capacitance decreased. In integrated circuit amplifiers, any reduction in the total capacitance is limited by the total of the parasitic junction capacitances set by the integrated circuit fabrication process and the size of the transistors included in the integrated circuit. To increase the slew rate without disturbing the bandwidth, input stage transconductance must be reduced by increasing the resistance of the input stage. This however undesirably results in higher input noise, more input offset voltage, and less open loop gain.
It is also known to use a current-feedback amplifier which typically provides excellent slew rate performance. Thus the closed loop bandwidth is independent of the noise gain, and depends on the feedback resistor. However, as is well known these types of amplifiers suffer from higher noise, higher input offset current, less precision and poor low level settling as well as other problems. See D. L. Smith, "High Speed Operational Amplifier Architectures",
Proceedings of the 1993 BCTM.
FIG. 3 shows a schematic diagram of a prior art current-feedback amplifier. (Reference symbols used in FIG. 3 that are identical to those in FIG. 1 or 2 do not refer to identical structures.) Here the input stage is a unity-gain buffer forcing the inverting input (-in) to follow the non-inverting input (+in). Any voltage imbalance of the inputs of this buffer causes the current to flow in or out of the inverting input. These currents are sensed internally to charge and discharge the internal compensation capacitors CT1 and CT2. The amount of current depends on the feedback resistor Rf2 which couples the output ("out") of the amplifier to its inverting input. Therefore the small-signal bandwidth of the amplifier, to a first approximation, depends on the time constant of the feedback resistor Rf2 and the total compensation capacitance CT1 plus CT2, and is independent of closed loop gain. See D. F. Bowers, "The Impact of New Architectures on the Ubiquitous Operational Amplifier"
Proceedings of the 1992 Workshop on Advances in Analog Circuit and Design in Europe.
For the amplifier shown in FIG. 3, any large input step creates momentarily a large error of voltage across the feedback resistor Rf2. The current available to charge and discharge the compensation capacitors CT1, CT2 is proportional to this voltage and inversely proportional to the value of the feedback resistance. This might suggest an unlimited slew rate; however, in reality a variety of second order effects limit the slew rate. Despite the high slew capability of such an amplifier, the Early effect of transistors of Q1 to Q4 causes poor CMMRR (common mode rejection ratio).
Therefore typically in the input stage of a class AB amplifier, during a slew when the input signal is rapidly increasing or decreasing in amplitude, there is undesirably a failure of the output signal to respond rapidly to the increase or decrease in the input signal. This is due to the limited current available to, in the amplifier of FIG. 3, transistors Q1 and Q2. The current available to transistors Q1 and Q2 is limited respectively by the constant current supplies I1, I2. This limits the capability of transistors Q3 and Q4 to respond adequately to a slew in the non-inverting input signal because current sources I1, I2 must charge or discharge the capacitances at respectively the bases of transistors Q3, Q4. These capacitances include the parasitic capacitances present between (1) the emitter of transistor Q2 and the collector of transistor Q3 (capacitance Cjc3) and (2) the emitter of transistor Q1 and the collector of transistor Q4 (capacitance Cjc4). This inability to respond rapidly is largely due to the parasitic capacitances present in transistors Q3, Q4 and the internal capacitances of current sources I1, I2 themselves. Thus there is a need for improvements in the slew rate performance of the input stage of an amplifier, given the minimum amount of total capacitance present in a typical amplifier, and without substantially increasing power consumption to provide higher supply current.
FIG. 4 shows schematically the input stage of a voltage feedback amplifier having the same deficiency as the amplifier of FIG. 3 in that the current available to output transistors Q5 and Q6, and hence their ability to respond to a high slew rate signal, is limited by the amount of current provided by constant current sources I3, I6 connected to the bases of transistors Q5, Q6 respectively. Note that the left hand portion of FIG. 4 shows the input stage of an amplifier; the output stage is depicted merely as the "Buffer".
It is to be understood that the NPN, PNP beta mismatch is a separate problem from that of slew rate performance.